1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a technique for preventing a protection film, a wiring layer and an interlayer insulating film in a scribe grid region serving as a boundary region between semiconductor element regions, from occurrence of internal separation, chipping or damage due to an impact caused by dicing in a semiconductor device assembling process.
2. Description of the Related Art
In manufacturing of a semiconductor device, conventionally, after completion of a diffusing step of forming a circuit of a semiconductor element, an assembling step of packaging the semiconductor element is performed. The assembling step includes a dicing step.
As a semiconductor wafer dicing method, commonly, blade dicing is adopted. In the blade dicing, an annular dicing saw, to which particles made of diamond or CNB (Cubic Boron Nitride) are stuck by a bond, is allowed to rotate at a high speed to thereby rupture a semiconductor wafer along a dicing lane serving as a region required for dicing (an actual dicing width of the dicing saw).
A conventional semiconductor wafer has a simple structure that a rigid interlayer insulating film is formed between wiring layers, and wiring layers and interlayer insulating films are small in number. Therefore, chipping or internal separation is hardly occurred in a dicing step of dicing a semiconductor wafer. If such a disadvantage is occurred, an extent of thereof is small. Hence, chipping or internal separation hardly causes reduction in yield of a semiconductor chip obtained by dicing and deterioration in reliability of the semiconductor ship.
In recent years, however, there arise some problems in a dicing step due to the following reasons.
As a technique for finely defining a process rule in a diffusion process is advanced, a boundary region (hereinafter, referred to as a “scribe grid region”) between semiconductor element regions on a semiconductor wafer is reduced in area. As a result, the scribe grid region has a little margin for dicing.
A PCM (Process Control Modulation) region becomes complicated and is increased in area. In order to effectively use a scribe grid region, the PCM region is formed on the scribe grid region, so that patterns of a wiring layer and an interlayer insulating film becomes complicated in the scribe grid region.
As a result, upon dicing a semiconductor wafer to divide each semiconductor element on the semiconductor wafer into individual semiconductor chips in a dicing step, a protection film or an interlayer insulating film suffers from chipping, internal separation or damage, resulting in reduction in yield of the semiconductor chip and deterioration in reliability of the semiconductor chip.
In order to solve the aforementioned problem, for example, there is proposed a semiconductor device illustrated in FIGS. 26, 27A and 27B. In this semiconductor device, a semiconductor wafer has the following structure. That is, a plurality of semiconductor element regions 12 and a plurality of scribe grid regions 13 are formed on a semiconductor substrate 11. In the respective semiconductor element regions 12 and scribe grid regions 13, hard interlayer insulating films 14 and soft insulating films 15 are laminated alternately and a protection film 14 is formed as an uppermost layer.
Then, a pair of seal rings 16 are formed in the scribe grid region 13 located between the semiconductor element regions 12, and a dicing region 17 is defined between the seal rings 16. The seal rings 16 make it possible to prevent the semiconductor element region 12 from occurrence of moisture intrusion, chipping and internal separation.
Each seal ring 16 is a thin metal wall for surrounding an outer periphery of the semiconductor element region 12, and is made of wiring metal, contact metal and the like.
On the other hand, JP2001-23937A discloses the following technique. Specifically, a plurality of integrated circuit chips are formed on a semiconductor wafer, and a crack propagation stopping part is provided in a seal region serving as a boundary between the integrated circuit chips. The crack propagation stopping part includes a continuous barrier wall, a sacrificial composite structure and a slot.
Further, JP2006-5288A discloses the following technique. Specifically, dummy vias are formed in respective layers of a dicing region. Herein, the dummy vias are formed at regular intervals in vertical and horizontal directions when being seen from above. With this configuration, even when cracking is occurred upon dicing, the dummy via prevents the cracking from propagating toward a seal ring.
However, due to advancement of a technique for finely defining a process rule in a diffusion process and advancement of a technique of planarization in the diffusion process, there arise the following problems that cannot be overcome by the aforementioned conventional techniques.
Specifically, a semiconductor wafer is planarized by CMP (Chemical Mechanical Polishing), so that an interlayer insulating film between wiring layers is reduced in thickness. Due to this planarization, frequencies of executing a step of forming a wiring layer and an interlayer insulating film are increased and, also, interlayer insulating films are increased in number. Consequently, a semiconductor wafer subjected to a diffusion process has a complicated configuration in regard to wiring layers and interlayer insulating films on a semiconductor substrate.
In addition, due to advancement of a technique for fine wiring in a diffusion process, a problem about wiring delay arising from increased inter-wiring capacitance becomes conspicuous. In order to suppress the wiring delay, an interlayer insulating film interposed between wiring layers is made of a low-k material (a low dielectric interlayer insulating film material) to achieve a low dielectric constant.
However, a film made of a low-k material is generally brittle and inferior in adhesiveness. Therefore, such a film is insufficient in mechanical strength as compared with a silicon oxide film adopted in a conventional semiconductor wafer. Consequently, internal separation is frequently occurred due to a damage upon dicing.
In light of the aforementioned disadvantages, it is difficult for the aforementioned conventional scribe grid structure to prevent a protection film and each wiring layer in a scribe grid region from occurrence of chipping, internal separation or damage upon dicing in a semiconductor device assembling process.
Conventionally, a seal ring is formed as a thin metal wall; however, if the metal wall is increased in thickness, a function of preventing the aforementioned internal separation or chipping can be enhanced.
However, since a seal ring is formed in a wiring forming step and a contact forming step in a diffusion process, a thickness thereof cannot be increased in terms of processing. Hence, internal separation or chipping must be prevented by a seal ring, which is a thin metal wall, upon dicing.